The Iron Album
| Vendor | Model | Model name | Arch | Interface | Clock | L1 cache | L2 cache |
|---|---|---|---|---|---|---|---|
| Sun | SM51 [501-2352] | SuperSPARC / SuperCache | SPARC/V8 | MBUS | 50MHz | 20K (64 B/l) IC + 16K (32 B/l) DC | 1MB (32 B/l) unified |
SPARCstation 20 PROM
SMCC SPARCstation 10/20 UP/MP POST version VRV3.43 (01/09/95)
CPU_#0 TI, TMS390Z55(3.0) 1Mb External cache
CPU_#1 ******* NOT installed *******
CPU_#2 ******* NOT installed *******
CPU_#3 ******* NOT installed *******
...
MXCC Register Test
MXCC E-Cache Tag RAM Test
MXCC E-Cache Data RAM Test (1 MB E$ DATA RAM, MXCC_CSR=00000000)
MXCC Non-Cache Block Zero Test
MXCC Non-Cache Block Copy Test
MXCC Cacheable Block Read Test
MXCC Cacheable Block Write Test
...
Cpu #0 TI,TMS390Z55
Cpu #1 Nothing there
Cpu #2 Nothing there
Cpu #3 Nothing there
...
SPARCstation 20 (1 X 390Z55), No Keyboard
ROM Rev. 2.22, 64 MB memory installed, Serial #7776049.
Ethernet address 8:0:20:76:a7:31, Host ID: 7276a731.
...
ok module-info
MBus : 40 MHz
SBus : 20 MHz
CPU#0 : 50 MHz SuperSPARC / SuperCache 2.x